Welcome to IEEE TCCA Email-Monthly, June 2003: 1. HPCA-10: International Symposium on High-Performance Computer Architecture Madrid, Spain, February 14-18, 2004 *Paper Due date: July 14, 2003 -Submitted by: Jose F. Martinez -Call For Papers: URL: http://www.ac.uma.es/hpca10/ 2. PACT 2003 Workshops: - New Orleans, LA September 27 - October 1, 2003, - AGridM 2003: Adaptive Grid Middleware - COLP 2003: Workshop on Compilers and Operating Systems for Low Power - MEDEA 2003: Memory Access Decoupled Architectures and Related Issues - SNAPI 2003: Storage Network Architecture and Parallel I/Os - SPDSEC 2003: Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing *Paper Due date: June 16, 2003 -Submitted by: Dieter Kranzlmueller, -Website: http://www.ccs.neu.edu/pact03/ -> Workshops 3. Computer Architecture Letters -Submitted by: Kevin Skadron -Website: 4. ASAP 2003, 14th IEEE International Conference on Application-specific Systems, Architectures and Processors *The Hague, The Netherlands, June 24-26, 2003 -Submitted by: Mainak Sen -CALL FOR PARTICIPATION: http://www.ece.rice.edu/asap2003/ 5. ERSA'03, The 2003 International Conference on ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS *June 23-26, 2003, Monte Carlo Resort, Las Vegas, Nevada, USA -Submitted by: Toomas Plaks -Final Program: http://www.scism.sbu.ac.uk/ERA/ersa.html ------- * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Professor Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Call for Papers HPCA-10 10th International Symposium on High-Performance Computer Architecture Madrid, Spain February 14-18, 2004 http://www.ac.uma.es/hpca10/ The International Symposium on High-Performance Computer Architecture provides a high quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit full papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to: + Processor architectures + Cache and memory architectures + Parallel computer architectures + Impact of VLSI scaling techniques + Novel architectures for emerging applications + Power-efficient architectures + High-availability architectures + High-performance I/O architectures + Embedded and reconfigurable architectures + Real-time architectures + Interconnect and network interface architectures + Network processor architectures + Innovative hardware/software trade-offs + Simulation and performance evaluation + Benchmarking and measurements Please check the conference web site for submission information: http://www.ac.uma.es/hpca10/ The submission should not exceed twelve pages in IEEE double column format. Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. The official submission deadline is July 14, 2003 at 9pm Pacific Time USA. An automatic extension of one week will be given without request. No further extensions will be given. Papers may be submitted for blind review at the option of the authors. Please indicate whether the paper is a student paper for best student paper nominations. Please submit proposals for workshops to the workshops chair by July 14, 2003. Important dates: Paper submission deadline: July 14, 2003 Workshop proposals due: July 14, 2003 Author notification: Oct. 6, 2003 Camera ready copy due: Nov. 3, 2003 ============================================== ---------------------------------------------------------------------------- Call for Papers: PACT 2003 Workshops: - AGridM 2003: Adaptive Grid Middleware - MEDEA 2003: Memory Access Decoupled Architectures and Related Issues - SNAPI 2003: Storage Network Architecture and Parallel I/Os - SPDSEC 2003: Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing Submission Deadline: June 16, 2003 ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- Call for Papers: PACT 2003 Workshops: - AGridM 2003: Adaptive Grid Middleware - COLP 2003: Workshop on Compilers and Operating Systems for Low Power - MEDEA 2003: Memory Access Decoupled Architectures and Related Issues - SNAPI 2003: Storage Network Architecture and Parallel I/Os - SPDSEC 2003: Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing Submission Deadline: June 16, 2003 ---------------------------------------------------------------------------- "PACT'03 takes spam seriously". We apologize, if you receive multiple copies of this call. If, for whatever reason, you do not wish to be included in this list, and/or do not wish to receive further announcements regarding PACT'03 or related topics, please contact me at pact2003@gup.jku.at. I will immediately remove your email address from the distribution list. (Additionally, we have taken all possible means to prevent illegal usage of the mailing list.) Yours sincerely, Dieter Kranzlmueller (PACT'03 Publicity Chair) ---------------------------------------------------------------------------- PACT 2003 Workshops The following workshops will be held together with PACT: - AGridM 2003: Workshop on Adaptive Grid Middleware - COLP 2003: Workshop on Compilers and Operating Systems for Low Power - MEDEA 2003: MEmory performance: DEaling with Applications, systems and architectures - SNAPI 2003: Workshop on Storage Network Architecture and Parallel I/Os - SPDSEC 2003: Workshop on Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing All workshops follow the following schedules: Submission Deadline: June 16, 2003 Author Notification: July 14, 2003 Final Papers Due: September 1, 2003 For submission procedures and special announcements, please check the individual workshop webpages for specific information. Please also check: http://www.ccs.neu.edu/pact03/ -> Workshops --------------------------------------------------------------------------- AGridM 2003: Workshop on Adaptive Grid Middleware Organizers: Wilson Rivera and Jaime Seguel, University of Puerto Rico Mayaguez, USA Scope: Grid computing research focuses on building a large-scale computing infrastructure by linking computing facilities at many distributed locations. By analogy with the electric power Grids, such systems are known as computational Grids. Significant effort has been spent in the design and implementation of middleware software for enabling computational Grids. These software packages have been successfully deployed and it is now possible to build clusters beyond the boundaries of a single local area network. However, the challenging problem of dynamically allocating resources in response to application requests for computational services remains unsolved. Adaptive middleware is software that resides between the application and the computer operating system and enables an application to adapt to changing availability of computing and networking resources. The purpose of this workshop is to provide an open forum for researchers from hardware and software areas to present, discuss, and exchange research-related ideas, results, and experiences in the area of adaptive middleware for computational Grids. Workshop webpage: http://ece.uprm.edu/agridm2003 --------------------------------------------------------------------------- COLP 2003: Workshop on Compilers and Operating Systems for Low Power Organizers: Diana Marculescu, Carnegie Mellon University, USA and J. Ramanujam, Louisiana State University, USA Scope: Power consumption has increasingly become important in computer systems. Current designs of processor cores are predicting power figures above 100 Watts. The management of power consumption while simultaneously delivering acceptable levels of performance is becoming a critical task with the proliferation of application domains such as wireless communication and embedded signal processing. In addition, it has become increasingly important to manage power consumption in high-performance, general purpose microarchitectures. It has been forecast that, without significant advances in design for low power, processors of the future will consume hundreds of watts of power. We believe that a synergistic hardware-software approach is required. A lot of attention has been paid to optimizing power at the circuit and gate levels. Recently, power optimizations at the architecture and software (i.e., compiler, operating system, and application) level have begun to receive increasing attention. The purpose of this workshop is to draw together researchers and practitioners concerned with compiler and operating system support for low power for a stimulating exchange of views. Presentations from invited speakers from both the industry and academia will provide insights into emerging issues related to this area of research. Workshop webpage: http://www.ece.lsu.edu/jxr/colp03.html --------------------------------------------------------------------------- MEDEA 2003: MEmory performance: DEaling with Applications, systems and architectures Organizers: Sandro Bartolini, University of Siena, Italy Pierfrancesco Foglia and Cosimo Antonio Prete, University of Pisa, Italy Scope: MEDEA-2003 aims to continue the high level of interest in the first three MEDEA Workshops held with PACT'00, PACT'01 and PACT'02. Due to the ever-increasing gap between CPU and memory speed, there is a great interest in evaluating and proposing processor, multiprocessor and system architectures dealing with the "memory wall" problem. In this scenario, memory performance issues can be better addressed when considering system architecture and application domain in a joint manner. In fact, it is the combined effect of the applications and the system on which they are executing that stresses the memory subsystem and pushes towards specific solutions. Typical architectural choices include single processor vs. multiprocessor solutions, single chip vs. COTS design, superscalar, multithreaded or VLIW architectures. Application domains encompass commercial (Web, DB, e-business, and multimedia), embedded (personal, mobile, automotive, automation and medical), networking applications, etc. The MEDEA-2003 Workshop wants to be a forum for academic and industrial people to meet, discuss and exchange their ideas and experience on the design and evaluation of architectures for embedded, commercial and general purpose systems. Main topics are memory performance issues and solutions in the various application domains. Workshop webpage: http://garga.iet.unipi.it/medea03/ --------------------------------------------------------------------------- SNAPI 2003: Workshop on Storage Network Architecture and Parallel I/Os Organizer: Qing (Ken) Yang, University of Rhode Island, USA Scope: Data are the "life-blood" of computing and the main asset of any organization. Therefore, disk I/O and data storage on which data reside are becoming "first class citizens" in today's information world. This workshop intends to bring together researchers and practitioners from academia and industry to discuss cutting edge research on parallel and distributed data storage technologies. By discussing ongoing research, the workshop will expose participants to the most recent developments in storage network architectures and parallel I/O. Workshop webpage: http://www.ele.uri.edu/tcca/SNAPI_CFP.html --------------------------------------------------------------------------- SPDSEC 2003: Workshop on Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing Organizers: Minyi Guo, University of Aizu, Japan Laurence Tianruo Yang, Francis Xavier University, Canada Scope: The field of parallel and distributed processing has obtained prominence through advances in electronic and integrated technologies beginning in the 1940s. Current times are very exciting and the years to come will witness a proliferation in the use of parallel and distributed systems, or supercomputers. The scientific and engineering application domains have a key role in shaping future research and development activities in academia and industry. The purpose of this workshop is to provide an open forum for computer scientists, computational scientists and engineers, applied mathematicians, and researchers to present, discuss, and exchange research-related ideas, results, works-in-progress, and experiences in the areas of architectural, compilation, and language support for problems in science and engineering applications. Workshop webpage: http://juliet.stfx.ca/people/fac/lyang/pact03-spdsec/ --------------------------------------------------------------------------- ============================================== Computer Architecture Letters is pleased to announce the publication of another paper online at our website, ; abstracts appear below. The papers will appear in print in our next paper issue. The print issues are distributed to the entire IEEE Computer Society TCCA membership, and e-mail notifications of newly accepted papers are sent on a regular basis to the TCCA and ACM SIGARCH memberships. Paper: R. Sendag, P.-f. Chuang, D. J. Lilja. "Address Correlation: Exceeding the Limits of Locality." Volume 2, May 2003. The objective of Letters is to publish short (4-page), timely articles of high-quality work. We are very much aware of the long delays in our field between submissions of manuscripts and their eventual appearance in print. We are doing something about that with this journal. After just over one year of operation, we have maintained an average turnaround time from submission to author notification of just one month, with an acceptance rate of 20%. We encourage the community to continue submitting papers to Letters. Submissions are welcomed on any topic in computer architecture, especially but not limited to: - Microprocessor and multiprocessor systems - Microarchitecture and ILP processors - Workload characterization - Performance evaluation and simulation techniques - Compiler-hardware and operating system-hardware interactions - Interconnect architectures - Memory and cache systems - Power and thermal issues at the architecture level - I/O architectures and techniques - Independent validation of previously published results - Analysis of unsuccessful techniques - Network and embedded-systems processors - Real-time and high-availability architectures - Reconfigurable systems The call for papers and instructions for submission can be found at Abstracts --------- R. Sendag, P.-f. Chuang, D. J. Lilja. "Address Correlation: Exceeding the Limits of Locality." Volume 2, May 2003. Abstract: We investigate a program phenomenon, Address Correlation, which links addresses that reference the same data. This work shows that different addresses containing the same data can often be correlated at run-time to eliminate a load miss or a partial hit. For ten of the SPEC CPU2000 benchmarks, 57 to 99% of all L1 data cache load misses, and 4 to 85% of all partial hits, can be supplied from a correlated address already found in the cache. Our source code-level analysis shows that semantically equivalent information, duplicated references, and frequent values are the major causes of address correlations. We also show that, on average, 68% of the potential correlated addresses that could supply data on a miss of an address containing the same value can be correlated at run time. These correlated addresses correspond to an average of 62% of all misses in the benchmark programs tested. ============================================== ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ASAP 2003 CALL FOR PARTICIPATION ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 14th IEEE International Conference on Application-specific Systems, Architectures and Processors The Hague, The Netherlands, June 24-26, 2003 http://www.ece.rice.edu/asap2003/ Program: http://www.ece.rice.edu/asap2003/program03.html Registration: https://newton.computer.org/conferences/asap03.nsf/ Hotel information: http://www.ece.rice.edu/asap2003/hotel.html The conference will cover the theory and practice of application-specific systems, architectures and processors. Areas for application-specific computing are many and varied. Some sample areas include information systems, signal and image processing, multimedia systems, high-speed networks, compression, graphics, and cryptography. Aspects of application-specific computing that are of interest include, but are not limited to: Application-specific systems: network computing, special-purpose systems, performance evaluation, design languages, compilers, operating systems, nanocomputing systems and applications, hardware/software integration, rapid-prototyping. Application-specific architectures: special-purpose designs, design methodology, CAD tools, fault tolerance, specifications and interfaces, networks-on-a-chip, hardware/software codesign, processor arrays, SoC, superscalar, multithreaded, VLIW, and EPIC architectures. Application-specific processors: digital signal processing, computer arithmetic, configurable/custom computing, implementation methodologies, new technologies, fine-grain parallelism, low-power designs, asynchronous hardware. The conference will feature a keynote speech by Ruby Lee entitled "Challenges in the Design of Security-Aware Processors," paper presentations, and recreational activities. The proceedings will be published by IEEE Computer Society Press. Conference Organizers ---------------------------- General Chairs: Ed Deprettere, Leiden University Shuvra Bhattacharyya, University of Maryland Program Chairs: Lothar Thiele, Swiss Federal Institute of Technology Zuerich (Systems) Alain Darte, Ecole Normale Superieure de Lyon (Architectures) Joseph Cavallaro, Rice University (Processors) Steering Committee: Jose Fortes, University of Florida S-Y Kung, Princeton University Michael Schulte, University of Wisconsin Earl Swartzlander, University of Texas Program Committee: Shail Aditya, HP Labs Mark Arnold, Lehigh University Magdy Bayoumi, University of Louisiana at Lafayette Neil Burgess, Cardiff University Peter Cappello, University of California at Santa Barbara Liang-Gee Chen, National Taiwan University Gerhard Fettweis, Dresden University of Technology Jose Fortes, University of Florida Guang Gao, University of Delaware Graham Jullien, University of Calgary Israel Koren, University of Massachusetts at Amherst S-Y Kung, Princeton University Tomas Lang, University of California at Irvine Ruby Lee, Princeton University Wayne Luk, Imperial College Elias Manolakos, Northeastern University John McCanny, Queen's University of Belfast Jean-Michel Muller, Ecole Normale Sup. de Lyon Praveen Murthy, Fujitsu Laboratories of America Tobias Noll, Aachen Institute of Technology Keshab Parhi, University of Minnesota at Twin Cities Peter Pirsch, University of Hannover Gang Qu, University of Maryland Patrice Quinton, IRISA, Campus de Beaulieu Sanjay Rajopadhye, Colorado State University Michael Schulte, University of Wisconsin-Madison Earl Swartzlander, University of Texas at Austin Juergen Teich, Paderborn University Mateo Valero, Technical University of Catalonia Pieter van der Wolf, Philips Research Laboratories Stamatis Vassiliadis, Delft University of Technology Ingrid Verbauwhede, University of California at Los Angeles Doran Wilde, Brigham Young University Roger Woods, Queen's University of Belfast Kung Yao, University of California at Los Angeles Pen-Chung Yew, University of Minnesota at Twin Cities -------------------------------------------------------------------------- ERSA'03 Schedule June 23 08:25 - 08:40am: MultiConference Opening Remarks Hamid R. Arabnia (General Chair, 2003 Int'l = MultiConference), University of Georgia, Athens, Georgia, USA (LOCATION: Lance Burton Theater) 08:40 - 09:40am: MultiConference Keynote Speaker: Prof. H. J. Siegel, Colorado State University, USA "On the Robustness of Resource Allocation for Parallel and Distributed Computing and Communications" (LOCATION: Lance Burton Theater) 09:40 - 10:25am: MultiConference Invited Talk: Prof. Barry Vercoe; Director, MIT Media Lab., MIT, USA = + Dr. Hidehito Kitamura, Taito Corp., Japan + Dr. Michael Haidar, Analog Devices Inc, USA "Multiprocessor Csound: Audio-Pro with Multiple DSP's = and Dynamic Load Distribution" (LOCATION: Lance Burton Theater) 10:25 - 11:25am: ERSA'03 (for MultiConference) Keynote Speaker: Nick Tredennick and Brion Shimamoto Gilder Technology Report, USA "The Rise of Reconfigurable Systems" (LOCATION: Lance Burton Theater) 11:25 - 12:30pm: LUNCH (On Your Own) 12:50 - 01:00pm: OPENING REMARKS Toomas Plaks (SBU, London, UK), ERSA Chair (LOCATION: Meeting Room G) 01:00 - 01:30pm: (Invited Talk) Collaborative and Reconfigurable Object Tracking Majid Sarrafzadeh UCLA, USA (LOCATION: Meeting Room G) FOCUSED SESSION 1ER: Operating Systems for Reconfigurable Hardware Chair: Marco Platzner, ETH, Zurich, Switzerland June 23, 01:30 - 02:50pm (LOCATION: Meeting Room G) 01:30 - 01:50pm: Hierarchical Run-Time Reconfiguration Managed by a Operating System for Reconfigurable Systems V. Nollet*, J-Y. Mignolet, T. A. Bartic, D. Verkest, S. Vernalde and R. Lauwereins IMEC, Belgium 01:50 - 02:10pm: An Improved Intermediate Representation for Datapath Generation Nico Kasprzyk*, Andreas Koch, UlrichGolze and Michael Rock Technical University of Braunschweig, Germany 02:10 - 02:30pm: A Configurable Hardware Scheduler for Real-Time Systems Mohamed Shalan* and Pramote Kuacharoen Georgia Institute of Technology, USA 02:30 - 02:50pm: The Impact of Routing Architecture on Reconfiguration Overheads Stephen M. Charlwood* and Steven F. Quigley University of Birmingham, UK 02:50 - 03:05pm: BREAK FOCUSED SESSION 2ER: Synthesis of Reconfigurable Systems Chair: Majid Sarrafzadeh, UCLA, USA June 23, 03:05 - 04:25pm (LOCATION: Meeting Room G) 03:05 - 03:25pm: A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers Jack Jean*, Xinzhong Guo, Fei Wang, Lei Song and Ying Zhang; Wright State University, USA 03:25 - 03:45pm: Code Parameterization for Satisfaction of QoS Requirements in Embedded Software K. Cooper*, Jia Zhou, Ma Hui, I-Ling Yen and Farokh Bastani University of Texas at Dallas, USA 03:45 - 04:05pm: Fast Design Space Exploration Method for Reconfigurable Architectures Lilian Bossuet*, Guy Gogniat and Jean-Luc Philippe LESTER - Centre de Recherche, France 04:05 - 04:25pm: Instance-Specific Solutions to Accelerate the CKY Parsing Jacir L. Bordim, Yasuaki Ito and Koji Nakano* Japan Advanced Institute of Science & Technology, Japan 04:25 - 05:30pm: DISCUSSION SESSION - ERSA (June 23) Short Papers + Regular Research Reports + Posters (For list of papers, refer to the end of ERSA'03 = schedule) (LOCATION: Meeting Room G + ...) June 24 08:20 - 08:50am: (Invited Talk) Altera FPGA Technology Provides Innovative Solution for Evolving Market Needs Razak Mohammedali Altera Corporation, San Jose, California, USA (LOCATION: Meeting Room G) FOCUSED SESSION 3ER: Configurable Systems-on-Chip Chair: Juergen Becker, Univ. of Karlsruhe, Germany June 24, 08:50 - 10:35am (LOCATION: Meeting Room G) 08:50 - 09:10am: An Interface Methodology for Retargettable FPGA Peripherals Tien_Lung Lee* and Neil W. Bergmann University of Queensland, Australia 09:10 - 09:30am: Co-Simulation of a Hybrid Multi-Context Architecture Rolf Enzler*, Christian Plessl and Marco Platzner Swiss Federal Institute of Technology Zurich (ETH) 09:30 - 09:50am: A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA J. R. Guo*, C. You, M. Chu, K. Zhou, R. P. Kraft and J. F. McDonald Rensselaer Polytechnic Institute, USA 09:50 - 10:20am: A Methodology to Implement Real-Time Applications on Reconfigurable Circuits Linda Kaouane*, Mohamed AKIL*, Yves Sorel** and Thierry Grandpierre* *Groupe ESIEE--Laboratoire A2SI, France **INRIA Rocquencourt--OSTRE, France 10:20 - 10:35am: BREAK 10:35 - 11:05am: (Invited Talk) Servers for Embedded Platform FPGAs Cameron Patterson XILINX Research Labs, USA (LOCATION: Meeting Room G) FOCUSED SESSION 4ER: Mobile Computing and Software Defined Radios Chair: Jeffrey Reed, Virginia Tech., USA June 24, 11:05am - 01:20pm (LOCATION: Meeting Room G) 11:05 - 11:25am: Montium - Balancing Between Energy-Efficiency, Flexibility and Performance Paul M. Heysters*, Gerard J.M. Smit and Egbert Molenkamp University of Twente, The Netherlands 11:25 - 11:55am: Mapping Wireless Communication Algorithms to a Reconfigurable Architecture G. K. Rauwerda, G. J. M. Smit, L. F. W. van Hoesel and P. M. Heysters University of Twente, the Netherlands 11:55 - 12:40pm: Lunch (On Your Own) 12:40 - 01:00pm: FPGA Signal Processing Chris Dick XILINX, Inc., USA 01:00 - 01:20pm: Next Generation Architecture for Heterogeneous Embedded Systems S. Murat Bicer*, Frank Pilhofer, Graham Bardouleau and Jeffrey Smith Mercury Computer Systems, Inc., Chelmsford, MA, USA 01:20 - 01:50pm: (Invited Talk) Latest Developments at Quicksilver Tech. Steven Guccione QuickSilver Tech., Inc., USA (LOCATION: Meeting Room G) FOCUSED SESSION 5ER: Java-Based Environments Chair: Cameron Patterson, XILINX Research Labs, USA June 24, 01:50 - 03:00pm (LOCATION: Meeting Room G) 01:50 - 02:10pm: JBits Based Fault Tolerant Framework for Evolvable Hardware A. P. Shanthi*, Balaji Vijayan, Manivel Rajendran, Senthilkumar Veluswami and Ranjani Parthasarathi Anna University, Chennai, India 02:10 - 02:30pm: A JBits-Based Incremental Design IDE with Non-Preemptive Refinement for Multi-Million Gate FPGAs Jing Ma* and Peter Athanas Virginia Tech, USA 02:30 - 03:00pm: JBits API for Virtex-II FPGAs=20 Prasanna Sundararajan XILINX, Inc., USA 03:00 - 06:20pm: ERSA'03 attendees are encouraged to attend = sessions/tracks belonging to other joint conferences that have the same scope as ERSA (Refer to the schedules for the = other conferences.) June 25 08:20 - 08:50am: (Invited Talk) PACT XPP Architecture in Adaptive System-on-Chip Integration Jurgen Becker Univ. of Karlsruhe, Germany (LOCATION: Meeting Room G) FOCUSED SESSION 6ER: Numeric Processing Chair: Maya Gokhale, Los Alamos National Laboratory, = USA June 25, 08:50 - 10:20am (LOCATION: Meeting Room G) 08:50 - 09:10am: FPGA Circuits for a Monte-Carlo Based Matrix Inversion Architecture O. Cadenas*, G. Megson* and T. Plaks** *University of Reading, Reading UK **South Bank University, London, UK 09:10 - 09:30am: Precision Modeling of Floating-Point Applications in Variable Bitwidth Computing Zhihong Zhao* and Miriam Leeser** *Alternative System Concepts, Inc., USA **Northeastern University, USA 09:30 - 09:50am: Energy-Efficient Disctrete Cosine Transform on FPGAs Ronald Scrofano*, Ju-Wook Jang** and Viktor K. = Prasanna* *University of Southern California, USA **Sogang University, Korea 09:50 - 10:20am: Towards an RCC-Based Accelerator for Computational Fluid Dynamics Applications William D. Smith* and Austars R. Schnore GE Global Research, USA 10:20 - 10:35am: BREAK FOCUSED SESSION 7ER: Adaptive Architectures and Hardware Chair: Steven Guccione, QuickSilver Tech., Inc., USA June 25, 10:35am - 12:05pm (LOCATION: Meeting Room G) 10:35 - 10:55am: Architecture of Reconfigurable Processor for Implementing Search Algorithms over Discrete Matrices Valery Sklyarov* and Iouliia Skliarova Aveiro University, Portugal 10:55 - 11:15am: A Reconfigurable Self-healing Embryonic Cell Architecture X. Zhang, G. Dragffy*, G. Pipe, N. Gunton and Q. M. Zhu University of the West of England, UK 11:15 - 11:35am: Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System Klaus Danne*, Christophe Bobda and Heiko Kalte University of Paderborn, Germany 11:35 - 12:05pm: A Reconfigurable Parallel Disk System for Filtering Genomic Banks D. Lavenier*, S. Guyetant*, S. Derrien* and S. Rubuni** *IRISA, France & **Brest University, France 12:05 - 12:15pm: CLOSING REMARKS Toomas Plaks (SBU, London, UK), ERSA Chair (LOCATION: Meeting Room G) 12:40 - 06:20pm: ERSA'03 attendees are encouraged to attend = sessions/tracks belonging to other joint conferences that have the same scope as ERSA (Refer to the schedules for the = other conferences.) June 26 08:20a - 06:20p: ERSA'03 attendees are encouraged to attend = sessions/tracks belonging to other joint conferences that have the same scope as ERSA (Refer to the schedules for the = other conferences.) 04:25 - 05:30pm: DISCUSSION SESSION - ERSA (June 23) Short Papers + Regular Research Reports + Posters (LOCATION: Meeting Room G + ...) O. Searching RC5 Keyspaces with Distributed Reconfigurable Hardware John P. Morrison, Padraig J. O'Dowd and Philip D. Healy* University College Cork, Ireland O. Using Flowpaths for the High-Level Synthesis of Reconfigurable Systems Darrin Hanna* and Richard E. Haskell Oakland University, USA O. Reconfigurable Computing and Active Networks Nikolaos G. Bartzoudis*, Alexandros G. Fragkiadakis, David J. Parish, Jose Luis Nunez and J. M. Stanford Loughborough University, UK O. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations Herbert Walder* and Marco Platzner Swiss Federal Institute of Technology Zurich (ETH) O. PyHDL: Hardware Scripting with Python Per Haglund*, Oskar Mencer**, Wayne Luk* and Benjamin Tai* *Imperial College, UK **Bell Labs, USA O. An Analysis Tool Set for Reconfigurable Media Processing Dasu Aravind Arizona State Univ, USA O. Dynamically Self-Reconfigurable Machine Learning Structure for FPGA Implementation Janusz A. Starzyk* and Yongtao Guo Ohio University, USA O. Egret - A Flexible Platform for Real-Time Reconfigurable Systems on Chip Neil Bergmann, John Williams* and Peter Waldek University of Queensland, Australia O. A Preliminary Study of Molecular Dynamics on Reconfigurable Computers Christophe Wolinski, Frans Trouw and Maya Gokhale* Los Alamos National Laboratory, USA O. Using Reconfigurable Computing to Accelerate Simulation Applications James M. McCollum*, Joseph M. Lancaster and Gregory D. Peterson University of Tennessee, Knoxville, USA O. A Fault Tolerant Multi-Agent System with Non-Deterministic Decision-Making for Task Allocation Maryam S. Mirian*, Majid Nili Ahmadabadi and Babak Nadjar Araabi; University of Tehran, Tehran, Iran O. Lower Bound Estimation on the Numbers of LUT Blocks and Micro-Registers for Time-Multiplexed FPGA Synthesis Seong Yong Ohm and Ki-Yeol Ryu*; Korea O. Producer and Consumer: Roles of a Microprocessor and a Configurable Logic in a Configurable SoC Seong-Yong Ahn*, Yo-Seop Hwang, Jea-Hong Shim and Jeong-A Lee; Korea O. Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications Timothy F. Oliver and Douglas L. Maskell* Nanyang Technological University, Singapore -------------------------------------------------------------------------- * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe